Principal Software Engineer (Verification of VIP using Verilog/SV/UVM )

*At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** *Job Description:** *Job Title: ( Verification of VIP using Verilog/SV/UVM – Ahmedabad )** *Cadence** is a pivotal leader in electronic design, building upon more than 30 years of computa