T
Lead RTL Engineer
Tessolve
kochi, India₹20,000–₹50,000/mo≈ AED 880-2.2K/moToday
IndiaEngineerFull Time
Skills Required
Git
Job Description
Job Description: Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL. Translate architectural specifications into synthesizable RTL code. Perform RTL simulations and debug logic issues. Collaborate with verification engineers to develop and review test plans an
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