FPGA Design Engineer

Role: FPGA RTL Design Engineer Loc: ECIL, Hyd Exp: 3 to 8 Yrs Skills VHDL & Xilinx (Artix/Kintex/Virtex) Vivado & ModelSim/QuestaSim UART, I2C, SPI, DDR, AXI, PCIe FPGA design, simulation & verification Defense/Aerospace Amit HR : 9866924395 *Required Candidate profile** expertise in Xil