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FPGA Architecture Developer

ACL Digital

Hyderabad, India₹35,000–₹100,000/moAED 1.5K-4.4K/moToday
IndiaDeveloperFull Time

Skills Required

PythonGit

Job Description

RTL FPGA Design Engineers Experience : 1-3 years Location : Hyderabad Expertise RTL Coding in Verilog, System Verilog or VHDL · Strong understanding of FPGA flow, Logic design, Digital design etc. · Knowledge in Xilinx FPGA architecture · Good Knowledge in Tcl, Python scripting. Interested,please sh