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Firmware Engineer — AI ASIC Accelerator

MBR Partners

Dubai, UAEAED 7,000-18,000/moYesterday
UAEIT & TechnologyFull Time

Skills Required

SapErpCommunication

Job Description

ASICFirmwareEngineer.FirmwareEngineer—AIASICAcceleratorWe’relookingforanexperiencedFirmwareEngineertobuildthelow-levelsoftwarefoundationforournext-generationAItrainingASIC.Inthisrole,you’llimplementthesecurebootchain,hardwarebring-upsequences,runtimemanagement,andhostcommunicationprotocolsthatbridgecustomsiliconandAIworkloads.You’llcollaboratewithsiliconarchitects,Linuxdriverengineers,securityteams,andsystemvalidationtodeliverproduction-gradefirmwareforenterpriseAIinfrastructure.Experiencenecessarytodothefollowing:Implementsecurebootchain(BootROM→PBL/SBL→RTOS),deviceattestation,andfieldupdatemechanismsBringupclocks,powerdomains,HBM,PCIe,NoC,andhigh-speedSerDesPHYsonemulation/FPGAandsiliconConfigure400GEthernetinterfaces(MAC/PCS/FEC)andcoordinatewithnetworkstackforRDMAoffloadDevelopruntimeservices:power/thermalcontrol,DVFS,watchdogs,RAS(ECC,crashdumps),errorrecoveryDesignmailboxprotocols,MSI/MSI-Xhandling,andDMAcoordinationwithLinuxdriverteamBuildunifiedtelemetryandeventtracingwithsynchronizeddatetimestamps(PTP/PHC)Supportmulti-diediscovery,linktraining,andtopologymanagementforchipletscalingWhatWe’reLookingFor:5+yearsembeddedfirmware(C/C++/Rust)onASIC/SoCorGPU-likeacceleratorsProvenexperiencewithPCIebring-up,HBM/DDRsubsystems,or100G+Ethernet—atleastoneisamustHands-onwithclock/powerdomainconfigurationandRASfeaturesComfortablewithschematics,registerspecs,JTAG/logicanalyzerdebuggingStrongdocumentationhabitsandsystemsthinkingacrossthefullstackRISC-V/ARM64,TrustZone/TEE,secureprovisioning,orQEMUpre-siliconexperienceisaplusFamiliarity with requirements traceability is valued#J-18808-Ljbffr