Field-Programmable Gate Arrays Engineer

RTL FPGA Design EngineersExperience : 1-3 yearsLocation : HyderabadExpertise RTL Coding in Verilog, System Verilog or VHDL · Strong understanding of FPGA flow, Logic design, Digital design etc. · Knowledge in Xilinx FPGA architecture · Good Knowledge in Tcl, Python scripting.Interested,please share