C
Design and Analysis Engineer
Confidential
Chennai, India₹20,000–₹50,000/mo≈ AED 880-2.2K/moToday
IndiaEngineerFull Time
Job Description
RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into S
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